DocumentCode :
3242255
Title :
Effect of the pattern structures on the charging damage during metal etching
Author :
Hasegawa, Akihiro ; Aoyama, Masaaki ; Ishida, Toshiyoki ; Nakamura, Moritaka ; Hashimoto, Koichi
Author_Institution :
ULSI Dev. Div., Fujitsu Ltd., Mie, Japan
fYear :
1999
fDate :
1999
Firstpage :
57
Lastpage :
60
Abstract :
Two dominant mechanisms govern charging damage: one is plasma nonuniformity and the other is topological effects of the wafer surface. Electron shading damage is well known as a typical topographical effect in plasma charging. In the case of electron shading, excess ion current flows through the gate oxide and the gate oxide reaches breakdown. Recently, phenomena such as local side etching of aluminum at particular space widths or bi-directional charging during plasma processing have been reported. Moreover, two kinds of charging damage have been distinguished: around the end point or during overetching, depending on the process conditions or hardware design. By using giant antenna probes, we revealed the possibility of bidirectional damage current flowing into the gate oxide. It was shown that, during metal overetching, negative charges could flow from the metal sidewall to the gate oxide. The negative current and charge-up voltage measured using the probe increased with increasing space width and electron temperature. Hence, open space and high electron temperature can induce major damage in real devices. These results can be explained by extending the electron shading effect (Hasegawa et al., 1998). In this paper, we measured the charging damage during metal etching, using the threshold voltage shift and subthreshold voltage swing shift of MOS transistors. We show the conditions for negative damage current generation at a MOS transistor connected to a sparse antenna
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; integrated circuit yield; plasma materials processing; sputter etching; surface charging; surface topography; CMOS process; MOS transistor; MOS transistors; around-end point charging damage; bi-directional charging; bidirectional damage current flow; charge-up voltage; charging damage; electron shading damage; electron shading effect; electron temperature; gate oxide; gate oxide breakdown; giant antenna probes; ion current flow; local side etching; metal etching; metal overetching; metal sidewall; negative charge flow; negative current; negative damage current generation; overetching; pattern structure effects; plasma charging; plasma charging damage; plasma nonuniformity; plasma processing; space widths; sparse antenna; subthreshold voltage swing shift; threshold voltage shift; topographical effect; wafer surface topological effects; Antenna measurements; Electrons; Etching; MOSFETs; Plasma applications; Plasma materials processing; Plasma temperature; Probes; Space charge; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Plasma Process-Induced Damage, 1999 4th International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-9651577-3-3
Type :
conf
DOI :
10.1109/PPID.1999.798808
Filename :
798808
Link To Document :
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