Title :
Overhead reduction techniques for hierarchical fault simulation
Author :
Harada, Eiji ; Pate, Janak H.
Author_Institution :
ULSI Syst. Dev. Labs., NEC Corp., Kawasaki, Japan
Abstract :
Overhead reduction techniques for hierarchical fault simulation are presented which reduce simulation overhead for the concurrent method and its expanded version, the Multi-List-Traversal method. The techniques include a one-pass fault simulation strategy, characteristic vectors, and contiguous concurrent machines. The cost of each process for the conventional and new methods is formulated for comparison. The methods were implemented in C, and experiments were conducted using ISCAS benchmark circuits. The results show that the new techniques make conventional concurrent fault simulators up to 4.9 times faster and also that the performance can be improved by fault ordering
Keywords :
ULSI; circuit analysis computing; combinational circuits; concurrent engineering; digital simulation; fault diagnosis; logic CAD; logic testing; multivalued logic circuits; ISCAS benchmark circuits; ULSI; characteristic vectors; concurrent method; contiguous concurrent machines; fault ordering; hierarchical fault simulation; logic test sequences; multi-list-traversal method; one-pass fault simulation strategy; overhead reduction techniques; simulation overhead; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Concurrent computing; Distributed computing; Hardware; High performance computing; Ultra large scale integration;
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
DOI :
10.1109/ATS.1995.485320