Modeling, design, virtual and physical prototyping, testing, and verification of a multifunctional processor queue for a single-chip multiprocessor architecture

Critical to run-time processor resource allocation, reconfiguration, and control of a reconfigurable heterogeneous single-chip multiprocessor architecture is a defined multifunctional queue required by each processor of the architecture. The multifunctional queue implements six functions required for control, resource allocation, and reconfiguration within the architecture. In addition to normal queue functionality of First In First Out (FIFO) operation and empty/full indicator, the multifunctional queue implements the additional non-common functions of indicating when queue depth has reached a programmable threshold level, it indicates queue occupancy level at all times, it continually indicates queue input rate over a programmable time interval, it continually indicates queue input rate change over a programmable time interval and it can implement a pseudo-RAM function. An analytic functional model of the queue is first presented then an organization, architecture and design is developed followed by the development of appropriate analytic real-time performance metrics for the queue. Both virtual and Field Programmable Gate array (FPGA) based prototypes of the queue are then developed and used for functional, maximum frequency, and/or performance model testing resulting in verification of desired queue functionality and performance. A contribution of the queue is its functional versatility which would allow its use in computer architectures or processors other than the described target architecture