Title :
Testable sequential circuit design: partitioning for pseudoexhaustive test
Author :
Shaer, Bassam ; Aurangabadkar, Kailash ; Agarwal, Nitin
Abstract :
In this study, we present an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The partitioning algorithm is based on the primary input cone and fanout value of each node in the circuit. We have developed an optimization process that can be used to find the optimal size of primary input cone and fanout values, to be used for partitioning a given circuit. Experimental results are presented to demonstrate the effectiveness of our work.
Keywords :
VLSI; logic CAD; logic partitioning; logic testing; sequential circuits; VLSI sequential circuit design; automated algorithm; fanout value; partitioning optimization; primary input cone; pseudoexhaustive testing; Circuit faults; Circuit testing; Computer science; Electrical fault detection; Fault detection; Logic testing; Partitioning algorithms; Sequential analysis; Sequential circuits; Very large scale integration;
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
DOI :
10.1109/ISVLSI.2003.1183484
