DocumentCode
3243227
Title
Testable sequential circuit design: partitioning for pseudoexhaustive test
Author
Shaer, Bassam ; Aurangabadkar, Kailash ; Agarwal, Nitin
fYear
2003
fDate
20-21 Feb. 2003
Firstpage
244
Lastpage
245
Abstract
In this study, we present an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The partitioning algorithm is based on the primary input cone and fanout value of each node in the circuit. We have developed an optimization process that can be used to find the optimal size of primary input cone and fanout values, to be used for partitioning a given circuit. Experimental results are presented to demonstrate the effectiveness of our work.
Keywords
VLSI; logic CAD; logic partitioning; logic testing; sequential circuits; VLSI sequential circuit design; automated algorithm; fanout value; partitioning optimization; primary input cone; pseudoexhaustive testing; Circuit faults; Circuit testing; Computer science; Electrical fault detection; Fault detection; Logic testing; Partitioning algorithms; Sequential analysis; Sequential circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN
0-7695-1904-0
Type
conf
DOI
10.1109/ISVLSI.2003.1183484
Filename
1183484
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