Simulation of PWB warpage during fabrication and due to reflow

As the electronic packaging industry moves towards the manufacturing of high density, multi layer PWBs, a key challenge, is the warpage of a PWB during fabrication, solder masking and reflow soldering process. Residual stresses caused by the coefficient of thermal expansion (CTE) mismatch between different board materials combined with thermo mechanical effects introduce the warpage. The excessive warpage not only adversely creates various manufacturing difficulties but also significantly causes serious reliability problems during normal operation. This paper investigates the warpage of large multi layered, high-density boards, and the effect of the layup on the warpage. Finite element analysis was used to model the thermally induced warpage of a 24 layer 492 mm×208 mm×4.88 mm PWB, due to reflow soldering. Wide ranges of, peak temperatures and cooling rates during reflow soldering were used to study the warpage of boards of varying thickness. The whole range of material properties of copper and FR4, which have been published, are used in this analysis. The warpage results, which were obtained at the end of the simulation, is presented. This analysis aid in identifying the impact of PWB layup on warpage and make recommendations to minimize warpage.