A new and accurate interconnection delay time evaluation in a general tree-type network

Author

Deschacht, D. ; Dabrin, C.

Author_Institution

Lab. d´´Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

fYear

1995

fDate

29 Aug-1 Sep 1995

Firstpage

359

Lastpage

364

Abstract

In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed a new analytical delay time expression for a general tree type network, with full incorporation of technology design parameters. A computationally simple technique is presented and comparisons with HSPICE simulation results show the accuracy of the developed model in timing verification

Keywords

integrated circuit interconnections; integrated logic circuits; logic CAD; timing; HSPICE simulation; delay time expression; distributed RC network; interconnection delay; interconnection lines; interconnection wires; timing verification; tree-type network; Capacitance; Circuit simulation; Computational modeling; Delay effects; Integrated circuit interconnections; Intelligent networks; Inverters; Logic gates; Timing; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Conference_Location

Chiba

Print_ISBN

4-930813-67-0

Type

conf

DOI

10.1109/ASPDAC.1995.486246

Filename

486246