DocumentCode
3247748
Title
A neural network approach to the placement problem
Author
Zamani, M. Saheb ; Hellestrand, G.R.
Author_Institution
Sch. of Comput. Sci. & Eng., Sydney Univ., NSW, Australia
fYear
1995
fDate
29 Aug-1 Sep 1995
Firstpage
413
Lastpage
416
Abstract
In this paper, we introduce a new neural network approach to the placement of gate array designs. The network used is a Kohonen self-organising map. An abstract specification of the design is converted to a set of appropriate input vectors fed to the network at random. At the end of the process, the map shows a 2-dimensional plane of the design in which the modules with higher connectivity are placed adjacent to each other, hence minimising total connection length in the design. The approach can consider external connections and is able to place modules in a rectilinear boundary. These features makes the approach capable of being used in hierarchical floorplanning algorithms
Keywords
circuit layout; circuit layout CAD; self-organising feature maps; Kohonen self-organising map; abstract specification; connectivity; external connections; floorplanning algorithms; gate array; neural network; neural network approach; placement problem; rectilinear boundary; Algorithm design and analysis; Circuits; Electronic mail; Neural networks; Neurons;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location
Chiba
Print_ISBN
4-930813-67-0
Type
conf
DOI
10.1109/ASPDAC.1995.486253
Filename
486253
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