Title :
A Comparative Analysis of Data-Driven Architectural Techniques for Low-Power Array Multipliers
Author :
Moshnyaga, Vasily G.
Author_Institution :
Fukuoka Univ., Fukuoka
Abstract :
Low-power multipliers are very important for reducing energy consumption of digital processing systems. Contrary to static design optimizations, the dynamic techniques exploit data variations on inputs and therefore are considered more power efficient. In this paper, we analyze dynamic power reduction techniques for array multipliers and present their experimental comparison on 16times16 bit multiplier design.
Keywords :
digital arithmetic; logic arrays; logic design; low-power electronics; multiplying circuits; 16times16 bit array multipliers; arithmetic operations; data-driven architectural techniques; digital processing systems; dynamic power reduction techniques; energy consumption; low-power array multipliers; Adders; CMOS digital integrated circuits; Computer science; Data analysis; Data engineering; Delay; Design optimization; Digital arithmetic; Energy consumption; Power engineering and energy;
Conference_Titel :
Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4244-2109-1
Electronic_ISBN :
1058-6393
DOI :
10.1109/ACSSC.2007.4487364
