Quasi-worst-condition built-in-self-test scheme for 4-Mb loadless CMOS four-transistor SRAM macro

Author

Takeda, K. ; Aimoto, Y. ; Nakamura, K. ; Masuoka, S. ; Ishikawa, K. ; Noda, K. ; Takeshima, T. ; Murotani, T.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

2001

fDate

14-16 June 2001

Firstpage

229

Lastpage

230

Abstract

We have developed a quasi-worst-condition Built-In-Self-Test (BIST) scheme capable of detecting defective cells. The effectiveness of the BIST, which is conducted at the time of power supply injection, is independent of ambient temperature. Measurement results indicate that defective cells detected in a wafer functional test in worst condition would also be detected with our newly developed BIST.

Keywords

CMOS memory circuits; SRAM chips; built-in self test; integrated circuit testing; macros; 4 Mbit; defective cell detection; loadless CMOS four-transistor SRAM macro; power supply injection; quasi-worst-condition built-in-self-test; wafer functional testing; Built-in self-test; CMOS logic circuits; CMOS process; CMOS technology; Fuses; Power supplies; Random access memory; Temperature measurement; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934248

Filename

934248

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3249155