A 800 MHz single cycle access 32 entry fully associative TLB with a 240 ps access match circuit

Author

Sumita, M.

Author_Institution

Microprocessor Dev. Center, Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan

fYear

2001

fDate

14-16 June 2001

Firstpage

231

Lastpage

232

Abstract

A high-speed content addressable memory (CAM) match circuit is the key for a system LSI in this digital network era, such as consumer electronics and digital communication. For example, a microprocessor with a memory management unit (MMU) has usually a translation look-aside buffer (TLB) including the CAM. The CAM is demanded small area, high speed, and also low power. In this paper we propose and study two types of CAM match circuit for a fully associative TLB.

Keywords

buffer circuits; content-addressable storage; high-speed integrated circuits; integrated memory circuits; low-power electronics; microprocessor chips; 240 ps; 800 MHz; LSI; MMU; content addressable memory; fully associative TLB; high-speed low-power CAM match circuit; memory management; microprocessor; translation look-aside buffer; Associative memory; CADCAM; Circuits; Computer aided manufacturing; Consumer electronics; Digital communication; Large scale integration; Memory management; Microprocessors; Power system management;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934249

Filename

934249

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3249171