Title :
Routing space estimation and safe assignment for macro cell placement
Author_Institution :
Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
29 Aug-1 Sep 1995
Abstract :
In this paper, a unified probabilistic-based estimation is firstly proposed for different kinds of channels. Furthermore, based on the estimation of channels, one safe routing space assignment is proposed to obtain a complete macro cell placement, and the time complexities of the safe routing space assignment is analyzed to be O(NlogN), where N is the number of macro cells in a macro cell placement. Finally, the experimental results show that the proposed approach has better accuracy for the assignment of routing space
Keywords :
VLSI; circuit layout CAD; circuit optimisation; computational complexity; integrated circuit layout; network routing; VLSI layout design; channel estimation; circuit layout CAD; experimental results; macro cell placement; probabilistic-based estimation; routing space assignment; routing space estimation; safe assignment; time complexity; Circuits; Design automation; Information science; Phase estimation; Phased arrays; Pins; Routing; Shape; Very large scale integration; Wire;
Conference_Titel :
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location :
Chiba
Print_ISBN :
4-930813-67-0
DOI :
10.1109/ASPDAC.1995.486413
