DocumentCode
3249641
Title
An analogue VLSI implementation of polychromous spiking neural networks
Author
Wang, Runchun ; Tapson, Jonathan ; Hamilton, Tara Julia ; Van Schaik, André
Author_Institution
Bioelectronics & Neurosci. Res. Group, Univ. of Western Sydney, Sydney, NSW, Australia
fYear
2011
fDate
6-9 Dec. 2011
Firstpage
97
Lastpage
102
Abstract
We present an analogue VLSI implementation of a polychronous network of spiking neurons. The network is capable of storing and retrieving spatial-temporal spike patterns. It consists of 14 leaky-integrate-and-fire neurons and corresponding axonal connections with programmable delays.
Keywords
CMOS integrated circuits; VLSI; neural nets; CMOS; VLSI implementation; axonal connections; polychronous spiking neural networks; programmable delays; spatial-temporal spike pattern retrieving; spatial-temporal spike pattern storing; spiking leaky-integrate-and-fire neurons; Delay; Fires; Firing; Generators; Neurons; Threshold current; Training; analogue VLSI; delay adaptation; polychronous network; spiking neurons;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP), 2011 Seventh International Conference on
Conference_Location
Adelaide, SA
Print_ISBN
978-1-4577-0675-2
Type
conf
DOI
10.1109/ISSNIP.2011.6146572
Filename
6146572
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