Analysis and characterization of single-poly floating gate device on 0.35-/spl mu/m partially-depleted SOI

Author

Durisety, Chandra Sekhar A ; Blalock, Benjamin J. ; Dufrene, Brian M.

Author_Institution

Electr. & Comput. Eng., Tennessee Univ., Knoxville, TN

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

91

Abstract

This paper presents the characterization results of a single-poly floating gate device (FGD) in 0.35 mum partially-depleted silicon-on-insulator (PDSOI) technology. Programmability of threshold voltage (V_TH) of these devices gives them a unique advantage in the development of post-process adjustable low offset operational amplifiers, highly accurate current mirrors, etc. This paper demonstrates a post-process trimmable current reference using these devices as resistive elements. A MATLAB model incorporating the tunneling parameters has been developed and the simulation results are found to match well with the experimental results

Keywords

MOSFET; reference circuits; semiconductor device models; silicon-on-insulator; 0.35 micron; partially-depleted silicon-on-insulator; resistive elements; single-poly floating gate device; threshold voltage programmability; trimmable current reference; tunneling parameters; Breakdown voltage; Capacitance; MOS devices; Mirrors; Operational amplifiers; Paper technology; Pulse measurements; Silicon on insulator technology; Threshold voltage; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594047

Filename

1594047