Symbolic verification of synthesized RTL using Boolean satisfiability and uninterpreted RTL transformations

We present a symbolic verification methodology to verify the register transfer logic (RTL) design generated during high-level synthesis (HLS) against the behavioral specification. The significant contributions of this paper are the following: (i) a symbolic verification methodology capable of verifying synthesis decisions at various stages of HLS; (ii) the use of SAT tool as the main verification engine - this enables the verification methodology to handle larger designs when compared with BDD-based methodologies; (iii) a exploitation of a set of uninterpreted RTL transformations that aid equivalence checking using SAT tools, and provide better diagnostics