Engineering systematic yield of fully-depleted SOI MOSFET

Author

Miura, N. ; Hayashi, H. ; Fukuda, K. ; Nishi, K.

Author_Institution

VLSI Res. & Dev. Center, Oki Electr. Ind. Co. Ltd., Tokyo, Japan

fYear

1999

fDate

1999

Firstpage

87

Lastpage

89

Abstract

We propose a new and effective SOI yield engineering methodology by sophisticated usage of 2D simulations. It is revealed by the methodology that, applying a limitation to threshold voltage yield and considering varied SOI layer thickness, the maximum current becomes substantially low. This trade-off relationship is balanced to obtain high maximum current and moderate source-drain breakdown voltage in acceptable turn around time

Keywords

MOSFET; elemental semiconductors; semiconductor device breakdown; semiconductor device models; semiconductor process modelling; silicon; silicon compounds; silicon-on-insulator; 2D simulations; SOI layer thickness; Si-SiO₂; device simulation; effective SOI yield engineering methodology; fully-depleted SOI MOSFET; high maximum current; maximum current; moderate source-drain breakdown voltage; process simulation; systematic yield; threshold voltage yield; trade-off relationship; Breakdown voltage; Data engineering; Etching; Intrusion detection; MOSFET circuits; Oxidation; Predictive models; Response surface methodology; Systems engineering and theory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 1999. SISPAD '99. 1999 International Conference on

Conference_Location

Kyoto

Print_ISBN

4-930813-98-0

Type

conf

DOI

10.1109/SISPAD.1999.799266

Filename

799266