Title :
A practical CMP profile model for LSI design application
Author :
Ohta, Toshiyuki ; Toda, Takeshi ; Ueno, Hisasi
Author_Institution :
ULSI Dev. Develop. Lab., NEC Corp., Kanagawa, Japan
Abstract :
We have developed a practical CMP model. The model is based on elastic mechanics. For practical use, some numerical treatments including a new time iteration method are developed. Using the model, numerical errors in a test chip are reduced to less than 1% with 5 minutes EWS calculation time. The simulated results agree with experiments within 5% error
Keywords :
chemical mechanical polishing; circuit CAD; integrated circuit design; iterative methods; large scale integration; semiconductor process modelling; stress analysis; 3D profiles; CAD tool; CMP profile model; LSI design application; Preston´s equation; elastic mechanics; elastic stress analysis; long-range uniformity; pattern density; reduced numerical errors; residual film thickness; stress response; test chip errors; time iteration method; Analytical models; Capacitance; Equations; Large scale integration; National electric code; Numerical models; Stress; Testing; Ultra large scale integration; Virtual manufacturing;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 1999. SISPAD '99. 1999 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
4-930813-98-0
DOI :
10.1109/SISPAD.1999.799294
