Suppression of anomalous leakage current in tunnel oxides by fluorine implantation to realize highly reliable flash memory

Author

Ushiyama, M. ; Satoh, A. ; Kume, H.

Author_Institution

Central Res. Lab., Hitachi Ltd, Tokyo, Japan

fYear

1999

fDate

14-16 June 1999

Firstpage

23

Lastpage

24

Abstract

By analyzing charge retention characteristics, we found that a flash memory with a critical tunnel oxide thickness has cells with anomalous threshold voltage (V/sub th/) lowering. We proposed a model where the traps near the poly-Si gate/tunnel oxide interface generate anomalous leakage current in the voltage range of 0-1 V, and the trapping/detrapping of electrons into the traps dominates the V/sub th/ distribution. We succeeded in suppressing the anomalous leakage current of the tunnel oxide by fluorine implantation into the Si substrate.

Keywords

MOS memory circuits; dielectric thin films; electron traps; flash memories; fluorine; integrated circuit measurement; integrated circuit reliability; ion implantation; leakage currents; tunnelling; 0 to 1 V; Si substrate; Si:F; SiO/sub 2/-Si:F; anomalous leakage current; anomalous leakage current suppression; anomalous threshold voltage lowering; charge retention characteristics; critical tunnel oxide thickness; electron detrapping; electron trapping; flash memory; fluorine implantation; high reliability flash memory; model; poly-Si gate/tunnel oxide interface traps; threshold voltage distribution; tunnel oxide; tunnel oxides; voltage range; Current measurement; Electrons; Flash memory; Laboratories; Leakage current; MOS capacitors; Stress measurement; Substrates; Time measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799321

Filename

799321