Title :
An 8-b 20-Msample/s pipelined A/D converter in 0.5-/spl mu/m CMOS with 7.8 ENOB
Author :
Savengsveksa, Vilaysack ; Heediley, P.L. ; Matthews, Thomas ; Ahmad, Kamel ; Negrete, Jose
Author_Institution :
Dept. of Electr. & Electron. Eng., California State Univ., Sacramento, CA
Abstract :
This paper presents an 8-b 20-Msample/s pipelined analog-to-digital converter (ADC) designed in 0.5-mum CMOS technology. On first silicon this converter achieved 7.8 effective-number-of-bits (ENOB), a peak differential-non-linearity (DNL) of -0.36LSB and integral-non-linearity (INL) of 0.35LSB
Keywords :
CMOS integrated circuits; analogue-digital conversion; 0.5 micron; 8 bit; CMOS technology; analog-to-digital converter; integral nonlinearity; peak differential nonlinearity; pipelined A/D converter; Analog-digital conversion; CMOS technology; Capacitors; Circuits; Clocks; Design for testability; Energy consumption; Logic testing; Sampling methods; Voltage;
Conference_Titel :
Circuits and Systems, 2005. 48th Midwest Symposium on
Conference_Location :
Covington, KY
Print_ISBN :
0-7803-9197-7
DOI :
10.1109/MWSCAS.2005.1594124
