Synthesis of opamps by manipulation of BBBs described under the standard of Verilog-AMS

It is presented a structured method for the synthesis of CMOS opamps, which explores all possibilities to interconnect basic building blocks (BBBs), described under the standard of Verilog-AMS. The synthesis procedure manipulates internal nodes, port nodes and global (external) nodes during the superimposing of BBBs, and updates all nodes to encapsulate all BBBs into one general macro-block, the opamp. The structure of the method consist of a library of BBBs described in Verilog-AMS, and the circuit synthesizer which accepts the required circuit performance from the user, like gain, bandwidth, slew rate, and impedance. The method returns an SPICE-file at the transistor level of abstraction. If input specifications are not fulfilled, the method searches for a new form to combine BBBs (new topology), according to a genealogical tree. Two examples are shown to appreciate the form in which the ports nodes, internal nodes and elements are updated. To verify that the method can synthesize functional circuits, SPICE simulations are carried out by using CMOS technology of 0.5 mum