DocumentCode :
3252733
Title :
A Nanoscale bSPIFET to Overcome CMOS Scaling
Author :
Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Lee, Tai-Yi ; Lin, Kao-Cheng
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung
fYear :
2006
fDate :
2-5 Oct. 2006
Firstpage :
85
Lastpage :
87
Abstract :
In this paper, we are working on a probe into the effects of gate length (Lg) variation upon the nanoscale silicon on partial insulator field-effect transistor with block oxide (bSPIFET) being use for deca-nanometer age
Keywords :
CMOS integrated circuits; field effect transistors; semiconductor device manufacture; silicon-on-insulator; CMOS scaling; Si; deca nanometer; gate length variation; nanoscale bSPIFET; nanoscale silicon partial insulator field effect transistor with block oxide; Conference proceedings; Doping; Etching; FETs; Immune system; Insulation; Nanoscale devices; Probes; Silicon on insulator technology; Sun;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
International SOI Conference, 2006 IEEE
Conference_Location :
Niagara Falls, NY
ISSN :
1078-621X
Print_ISBN :
1-4244-0289-1
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2006.284445
Filename :
4062893
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3252733
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