Design and implementation of a bitstream parsing coprocessor for MPEG-4 video system-on-chip solution

Author

Chang, Yung-Chi ; Chang, Hao-Chieh ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2001

fDate

2001

Firstpage

188

Lastpage

191

Abstract

In this paper, the hardware-oriented bitstream structure analysis and an efficient and flexible bitstream parsing processor are presented. The analysis of MPEG-4 video bitstream structure based on RISC model explores requirement and design constraint for bitstream-level processing. It shows that conventional RISC is not efficient enough for bitstream parsing. An efficient instruction set optimized for bitstream processing is designed and the hardware architecture can be reconfigured for various applications. Compared with 160 MOPS required by a RISC, the proposed architecture needs only about 27 MOPS to parse an MPEG-4 video bitstream at high bit-rate as about 40 Mbit/s, which is about 6 times speedup. The impact of the proposed architecture on video applications is to enhance and extend the processing for bit domain translation and related real time applications

Keywords

application specific integrated circuits; coprocessors; real-time systems; video signal processing; 40 Mbit/s; MPEG-4 video; RISC model; bit domain translation; bitstream parsing coprocessor; design constraint; hardware-oriented bitstream structure analysis; instruction set; real time applications; system-on-chip solution; video applications; Coprocessors; Data compression; Decoding; Design optimization; Digital signal processing; Hardware; MPEG 4 Standard; Reduced instruction set computing; System-on-a-chip; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

0-7803-6412-0

Type

conf

DOI

10.1109/VTSA.2001.934516

Filename

934516