Testing FPGAs using JBits RTP cores

Author

Niamat, M.Y. ; Attravanam, K.M. ; Alam, M.

Author_Institution

Toledo Univ., OH

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1131

Abstract

In this paper, we present a fault-testing technique for field programmable gate arrays (FPGAs) that is based on the features offered by Java Bits (JBits). Our technique can detect single and multiple stuck at faults, and is capable of detecting the faulty CLB within the FPGA. The algorithm proposed for testing the faults in the CLB utilizes the unified-library primitives and the run-time parameterizable (RTP) cores of the JBits programming language. The method also explores the object-oriented approach of the Java programming language used in JBits. It has the capability of providing run-time fault avoidance in FPGAs based on the faults detected during the testing process. Since JBits involves programming directly at the bitstream level, the proposed method offers additional advantages over traditional testing techniques

Keywords

Java; electronic engineering computing; fault diagnosis; field programmable gate arrays; logic testing; object-oriented programming; software libraries; FPGA testing; JBits RTP cores; JBits programming language; Java Bits; Java programming language; ULPrimitives; fault testing; field programmable gate arrays; object-oriented approach; run-time fault avoidance; run-time parameterizable cores; runtime reconfiguration; stuck-at-faults; unified-library primitives; Circuit faults; Circuit testing; Computer languages; Databases; Fault detection; Field programmable gate arrays; Logic arrays; Logic devices; Reconfigurable logic; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594305

Filename

1594305