A new methodology in power estimation in CMOS combinational circuits at logic level

Nowadays accurate and fast power estimation of CMOS digital circuits during the design phase are required to guide power optimization techniques employed to reach stringent power specifications. Logic-level power estimation tools, such as those available in the SIS|7| frameworks are able to calculate accurately the switching activity in a given delay model. However, capacitance and delay modeling is crude. We propose new models for the input and output capacitances of CMOS logic gates complex based upon Sidinei and Joao (2004), taking into account the gate´s internal capacitances extracted from layout. The gotten results in the circuit´s benchmarks show a good agreement of the logic-level estimates and ELDO of the MENTOR Graphics, with up to 7.39% error in power estimation and a faster of CPU time.