High speed I/O circuit design in multiple voltage domains

Designing I/O drivers and receivers that must work across multiple voltage domains has several unique circuit-design challenges. One challenge is limitations due to process silicon breakdown voltage. A second disadvantage is the need to transition voltage levels. This is typically done with differential amplifier receivers, special high voltage N or P devices, external pull-ups, or voltage translators. Due to differences in switching levels, matching T_CO delays though identical receivers in different voltage domains will require additional consideration. Finally, system level simulations of chips crossing multiple voltage domains require 4 terminal devices, non-single global power supply nodes, and must handle multiple process technology files