DocumentCode :
3255886
Title :
Scheduling a reservation primitive for effective latency hiding in DSM
Author :
Hirota, M. ; Yamazaki, T. ; Yonezawa, N. ; Wada, K.
Author_Institution :
Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan
fYear :
1999
fDate :
1999
Firstpage :
601
Lastpage :
604
Abstract :
Distributed shared memory (DSM) systems potentially have both performance scalability and good programmability. However, they also have a drawback in their difficulty in overlapping computation with inter-processor communication. For DSM systems, we propose a novel coherence protocol called Selective Validity Control (SVC) protocol. In the SVC protocol, a new memory access operation called a link access is introduced to hide the read miss latency and to rearrange allocation for shared data. However, in order to have a link access work effectively, it has to be scheduled appropriately. The paper proposes a scheduler that collects and analyzes memory accesses of an application program, and automatically schedules link accesses. The effectiveness of the link access is also described. To evaluate the performance of the scheduler, a trace-driven simulator for a DSM system has been developed. Bitonic sort and FFT programs from the SPLASH-2 benchmark suite are executed on the simulator. The results of the evaluation show that the read miss penalty and overall execution time can be reduced by using link access operations scheduled by our proposed scheduler
Keywords :
distributed shared memory systems; fast Fourier transforms; memory protocols; message passing; processor scheduling; resource allocation; sorting; DSM system; FFT programs; SPLASH-2 benchmark suite; SVC protocol; Selective Validity Control protocol; application program; bitonic sort; coherence protocol; distributed shared memory systems; execution time; inter-processor communication; latency hiding; link access operations; memory access operation; memory accesses; performance scalability; programmability; read miss latency; read miss penalty; reservation primitive scheduling; shared data allocation; trace-driven simulator; Access protocols; Coherence; Communication system control; Control systems; Delay; Electronic mail; Scalability; Static VAr compensators; Switches; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Computers and Signal Processing, 1999 IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-5582-2
Type :
conf
DOI :
10.1109/PACRIM.1999.799609
Filename :
799609
Link To Document :
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