Title :
Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI
Author :
Ng, R. ; Udrea, F. ; Sheng, K. ; Ueno, K. ; Amaratunga, G.A.J. ; Nishiura, M.
Author_Institution :
Dept. of Eng., Cambridge Univ., UK
Abstract :
This paper examines for the first time the possibility of the Super Junction (SJ) concept to realise lateral device structures on SOI with high breakdown voltage and low on-resistance for use in power integrated circuits (PICs). More specifically, a novel structure based on an unbalanced SJ (USJ) configuration is proposed and investigated using the 3D-device simulator, DAVINCI. The physics of the SJ related structure is described in detail and is shown to rely on a truly three dimensional RESURF effect to achieve high voltage blocking capability-hence the acronym 3D-RESURF. It is also shown that a suitable choice of n and p stripe geometry, enables breakdown voltage in excess of 600 volts to be realised on SOI technology with 4 μm of buried oxide (BOX). Methods for optimising the breakdown capability of the proposed structure are also presented
Keywords :
buried layers; power MOSFET; power integrated circuits; semiconductor device breakdown; semiconductor device models; silicon-on-insulator; 3D device simulator; 600 V; DAVINCI; SOI; USJ/3D-RESURF; breakdown voltage; buried oxide; lateral device; on-resistance; power MOSFET; power integrated circuit; three-dimensional RESURF effect; unbalanced super junction; voltage blocking; Circuit simulation; Electric breakdown; Electric resistance; Geometry; MOSFET circuits; Optimization methods; Physics; Power integrated circuits; Research and development; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on
Conference_Location :
Osaka
Print_ISBN :
4-88686-056-7
DOI :
10.1109/ISPSD.2001.934637