DocumentCode
3256702
Title
Modeling and optimization of mixed logic circuits: the CMOS/CPL combination
Author
Wan, Yuanzhong ; Shams, Maitham
Author_Institution
Carleton Univ., Ottawa, Ont., Canada
fYear
2004
fDate
6-8 Dec. 2004
Firstpage
421
Lastpage
424
Abstract
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. In this paper, the combination of standard CMOS with CPL is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain´s propagation time and drive capability.
Keywords
CMOS logic circuits; buffer circuits; circuit optimisation; delay circuits; integrated circuit design; integrated circuit modelling; logic design; CMOS buffers; CMOS-complementary pass transistor logic circuits; delay circuits; integrated circuit design; logic design; mixed logic circuit modeling; mixed logic circuit optimization; single technology logic circuits; CMOS digital integrated circuits; CMOS logic circuits; Capacitance; Delay; Inverters; Logic circuits; MOS devices; MOSFETs; Semiconductor device modeling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
Print_ISBN
0-7803-8656-6
Type
conf
DOI
10.1109/ICM.2004.1434603
Filename
1434603
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