An Area-Time Efficient Architecture for 16 x 16 Decimal Multiplications

With growing demands of decimal computations in scientific, financial and many other key applications, area-time efficient hardware implementation of decimal arithmetic is desired. In this paper, we present a parallel architecture for the fixed-point decimal multiplications based on the 8421 BCD representation. By reducing the entries of partial product pre-computations and using a tree structure with carry-look ahead adders (CLAs) as opposed to carry-save adders (CSAs), a significant speedup of the partial product generations (PPGs) and partial product accumulations can be achieved, while at the same time, the hardware overhead can be reduced. The × decimal multiplier using the proposed architecture with a TSMC 90nm technology compares favorably against three other best known decimal multiplier designs in terms of delay-area product.