Finite state machine synthesis with fault tolerant test function

The authors propose a new method of synthesizing programmable logic array (PLA)-based finite-state machines with fault tolerant test machines. The procedure allows arbitrary state encoding. This can be exploited to achieve other objectives like minimizing the area of the PLA. Also, they do not assume an explicit reset state, and test generation does not require traversal of state transition programs. The procedure guarantees bounded-length test sequences for combinationally irredundant crosspoint faults. Experimental results on the MCNC logic synthesis workshop finite-state machine benchmark set showed the practicality of the proposed approach