Splitting of RC-network for accurate model reduction

Reduction of an extracted RC-network is an important pre-processing step for techniques such as timing and crosstalk noise analysis of VLSI circuit. In a previous paper, we have described a method for reducing an RC-network to a simplified circuit. The experience shows that the accuracy of the method is satisfying but the computation time is not reasonable. In this paper, we propose to split the initial RC-network in order to decrease the computation time.