Performance of Parallel Prefix Adders implemented with FPGA technology

Parallel Prefix Adders have been established as the most efficient circuits for binary addition. Their regular structure and fast performance makes them particularly attractive for VLSI implementation. The classical parallel prefix adder structures that have been proposed over the years optimize for logic depth, area, fan-out and interconnect count of the logic circuits. This paper investigates the performance of parallel prefix adders implemented with FPGA technology. We report on the area requirements and critical path delay for a variety of classical parallel prefix adder structures.