• DocumentCode
    3259294
  • Title

    Finite element analysis of hygrothermally induced stresses in plastic IC packages

  • Author

    Yi, Sung ; Goh, Jing Sua ; Yang, Ji Cheng

  • Author_Institution
    Sch. of Mech. & Production Eng., Nanyang Technol. Univ., Singapore
  • fYear
    1995
  • fDate
    27 Nov-1 Dec 1995
  • Firstpage
    32
  • Lastpage
    39
  • Abstract
    In the present study, the moisture and temperature distributions and residual stresses inside plastic encapsulated IC packages are evaluated in order to asses product reliability. Numerical procedures based on finite element analyses are presented to calculate the hygro-thermally induced deformations and stresses in plastic IC packages during the surface mounting process preceded by the moisture soaking test. For example residual stresses in thin LOC (Lead-On-Chip) TSOP packages during the reflow soldering process preceded by the 168 hours 85°C/85% RH moisture soaking test have been studied. Numerical results show that when TSOP packages undergo the reflow soldering process substantially high tensile σ2 stresses arose in the silicon chip while high compressive stresses were in the encapsulant below the chip. Such high compressive and tensile stress development in the silicon chip and encapsulant below the chip is responsible for the delamination and popcorn crack. The results also show that the magnitudes of residual stresses in IC packages may depend not only on the magnitude of loading but also on the loading history due to the hygro-thermo-viscoelastic behavior of plastic mold compound materials
  • Keywords
    encapsulation; environmental degradation; finite element analysis; integrated circuit packaging; moisture; plastic packaging; reflow soldering; surface mount technology; thermal stresses; LOC TSOP packages; delamination; encapsulant; finite element analysis; hygrothermally induced stresses; moisture distribution; moisture soaking test; mold compounds; plastic IC packages; popcorn crack; reflow soldering; reliability; residual stresses; silicon chip; surface mounting; temperature distribution; viscoelasticity; Compressive stress; Finite element methods; Integrated circuit testing; Moisture; Plastic integrated circuit packaging; Reflow soldering; Residual stresses; Silicon; Temperature distribution; Tensile stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the
  • Print_ISBN
    0-7803-2797-7
  • Type

    conf

  • DOI
    10.1109/IPFA.1995.487592
  • Filename
    487592