A flexible MPEG audio decoder layer III chip architecture

Moving Pictures Expert Group (MPEG) audio Layer III is the most advanced standard for digital audio compression. The high coding gain of the standard is due to its time to frequency mapping section, which is also the most compute intensive part of the audio coder. It has been shown in the literature that the Discrete Cosine Transform (DCT) proposed in the standard for the filterbank section could be implemented using the Fast Hartley Transform (FHT) in order to reduce the amount of computations and memory accesses. In this paper, an efficient approach is proposed for implementing the synthesis filterbank of the MPEG audio Layer III. The approach is based on a mixed radix FHT for implementing the Inverse Modified Discrete Cosine Transform (IMDCT) section and a radix-2 FHT for the subband decoding section. A high throughput pipeline VLSI architecture is designed for implementing the proposed approach. The architecture has been simulated and verified using the Cadence Verilog-XL simulator