DocumentCode
3260146
Title
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices
Author
Katsuki, Kazuya ; Kotani, Manabu ; Kobayashi, Kazutoshi ; Onodera, Hidetoshi
Author_Institution
Graduate Sch. of Informatics, Kyoto Univ.
fYear
2006
fDate
24-27 Jan. 2006
Abstract
It is possible to enhance speed and yield of reconfigurable devices utilizing WID variations. An LUT array LSI is fabricated on a 90nm process to measure WID and D2D variations. Performance fluctuations are measured by counting the number of LUTs through which a signal is passing within a certain time. D2D and WID variations are clearly observed by the measurement
Keywords
integrated circuit measurement; integrated circuit yield; large scale integration; logic arrays; table lookup; 90 nm; D2D variations; LUT array LSI; WID variations; reconfigurable devices; speed enhancement; yield enhancement; Clocks; Degradation; Flip-flops; Fractals; Large scale integration; Logic arrays; Semiconductor device measurement; Table lookup; Time measurement; Velocity measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location
Yokohama
Print_ISBN
0-7803-9451-8
Type
conf
DOI
10.1109/ASPDAC.2006.1594661
Filename
1594661
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