A 52mW 1200MIPS compact DSP for multi-core media SoC

Author

Ou, Shih-Hao ; Lin, Tay-Jyi ; Huang, Chao-Wei ; Kuo, Yu-Ting ; Chao, Chie-Min ; Liu, Chih-Wei ; Jen, Chein-Wei

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Taiwan

fYear

2006

fDate

24-27 Jan. 2006

Abstract

This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive micro-architecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3× performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18μm 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.

Keywords

C language; CMOS integrated circuits; digital signal processing chips; instruction sets; silicon; system-on-chip; 0.18 micron; 314 MHz; 52 mW; CMOS technology; DSP core; Si; automatic software generator; data centric instruction set; dual-core application processors; hardware design; microarchitecture; multicore media SoC; programmable core; signal processing tasks; CMOS technology; Chaotic communication; Digital signal processing; Hardware; Instruction sets; Microarchitecture; Process design; Reduced instruction set computing; Silicon; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 2006. Asia and South Pacific Conference on

Print_ISBN

0-7803-9451-8

Type

conf

DOI

10.1109/ASPDAC.2006.1594665

Filename

1594665