DocumentCode
3260269
Title
Configurable multi-processor architecture and its processor element design
Author
Nishimura, Tsutomu ; Miki, Takuji ; Sugiura, Hiroaki ; Matsumoto, Yuki ; Kobayashi, Masatsugu ; Kato, Toshiyuki ; Eda, Tsutomu ; Yamauchi, Hironori
Author_Institution
VLSI Center, Ritsumeikan Univ.
fYear
2006
fDate
24-27 Jan. 2006
Abstract
We developed an application specific multi-processor generation system intended for realtime applications. In this system, we adopted a distributed memory type multi-processor architecture with hierarchical tree network as a configurable multiprocessor which can be adapted to various scale systems flexibly. We have also developed a configurable multi-processor prototype as LSI chips with the 0.18 mum CMOS standard cell technology
Keywords
CMOS integrated circuits; large scale integration; microprocessor chips; multiprocessing systems; real-time systems; 0.18 micron; CMOS standard cell technology; LSI chips; application specific multi-processor generation system; configurable multiprocessor; distributed memory architecture; hierarchical tree network; realtime system; CMOS technology; Circuit testing; Clocks; Electronic design automation and methodology; Hardware design languages; Large scale integration; Multiprocessing systems; Pins; Process design; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location
Yokohama
Print_ISBN
0-7803-9451-8
Type
conf
DOI
10.1109/ASPDAC.2006.1594668
Filename
1594668
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