• DocumentCode
    326033
  • Title

    A parallel decoding scheme for turbo codes

  • Author

    Hsu, Jah-Ming ; Wang, Chin-Liang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    4
  • fYear
    1998
  • fDate
    31 May-3 Jun 1998
  • Firstpage
    445
  • Abstract
    The recursive computations in the MAP-based decoding of turbo codes usually introduce a significant amount of decoding delay. In this paper, we present a method for reducing the decoding delay by means of segmenting a block into several sub-blocks, which are partially overlapped. The proposed sub-block segmentation scheme allows for the parallel decoding of each component code by using several sub-block decoders. The number of steps for the recursive computations in each sub-block decoder is reduced to O(N/W), where W is the number of segmented sub-blocks. The decoding delay is approximately one-Wth that of a conventional MAP-based turbo-coding system. The cost paid is a slight degradation in bit error rate performance and a reasonable increase in hardware complexity
  • Keywords
    concatenated codes; convolutional codes; decoding; delays; error correction codes; error statistics; iterative methods; parallel processing; BER performance; MAP-based decoding; bit error rate; decoding delay reduction; parallel decoding scheme; recursive computations; sub-block segmentation scheme; turbo codes; Bit error rate; Convolutional codes; Costs; Degradation; Delay; Error correction codes; Hardware; Iterative algorithms; Iterative decoding; Turbo codes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    0-7803-4455-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.1998.698923
  • Filename
    698923