Modification of logic on ASIC devices

The author describes the modification of control logic on a 1 μm two layer metal ASIC device. The work was performed using focused ion beam (FIB) techniques to remove and deposit interconnect material. The task involved the modification of connections to four gates, requiring seven disconnections and the deposition of seven new connections, the longest of which was almost 500 μm. The task was successfully completed on two 132 pin PQFP packaged devices at FEI Europe in November 1991. This technique is suitable for the modification of prototype ASIC devices as it offers a quick and relatively inexpensive verification of design modifications prior to incurring the costs and delays associated with a second (or third) pass of the silicon