DocumentCode :
3260962
Title :
Spec-based flip-flop and latch repeater planning
Author :
Hon, Man Chung
Author_Institution :
Intel Corp., Santa Clara, CA
fYear :
2006
fDate :
24-27 Jan. 2006
Abstract :
Shrinking process geometries and frequency scaling give rise to an increasing number of interconnects that require multiple clock cycles. This paper explores efficient techniques to insert flip-flops and latches to meet pre-determined latency and margin constraints at the receivers. Previous approaches push timing margins to either ends of interconnect. We present an O(n log n)-time algorithm to insert flip-flops that evens out timing margins across the entire interconnect, resulting in more robust designs and faster design convergence. An O(n log n)-time extension to handle symmetric, two-phases latches is also presented. Experimental results verify the correctness and practicality of our approach
Keywords :
flip-flops; integrated circuit design; integrated circuit interconnections; logic design; timing; frequency scaling; latch repeater planning; multiple clock cycles; shrinking process geometry; spec-based flip-flop; time algorithm; two-phases latches; Algorithm design and analysis; Clocks; Convergence; Delay; Flip-flops; Frequency; Geometry; Repeaters; Robustness; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-9451-8
Type :
conf
DOI :
10.1109/ASPDAC.2006.1594703
Filename :
1594703
Link To Document :
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