ROTCO: a reverse order test compaction technique

In this paper, the authors consider the problem of reducing the test set sizes for single stuck-at faults in combinational logic circuits. They report on an alternative to the conventional reverse order fault simulation, called reverse order test compaction (ROTCO). The proposed procedure processes a test set obtained by an existing test generator, with the sim of reducing the test set size. Unlike reverse order fault simulation, the proposed procedure allows the test vectors to be changed in order to increase the flexibility in detecting faults detected by earlier vectors, thereby potentially removing tests that cannot be removed by reverse order fault simulation. Experimental results for ISCAS-85 and PLA benchmark circuits are presented to demonstrate the effectiveness of the proposed procedure