Title :
A fast logic simulator using a look up table cascade emulator
Author :
Nakahara, Hiroki ; Sasao, Tsutomu ; Matsuura, Munehiro
Author_Institution :
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka
Abstract :
This paper shows a new type of a cycle-based logic simulation method using a look-up table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascades through BDD (binary decision diagram). Then, it stores LUT data to the memory of an LUT cascade emulator. Next, it generates the C code representing the control circuit of the LUT cascade emulator. And, finally, it converts the C code into the execution code. This method is compared with a levelized compiled code (LCC) simulator with respect to the simulation time and setup time. Although we used standard PC to simulate the circuit, experimental results show that this method is 12-64 times faster than the LCC
Keywords :
binary decision diagrams; circuit simulation; logic simulation; table lookup; BDD; C code generation; LCC simulator; LUT cascade; binary decision diagrams; control circuit; execution code; fast logic simulator; levelized compiled code; look up table cascade emulator; Circuit simulation; Computational modeling; Computer science; Discrete event simulation; Logic circuits; Logic gates; Rails; Registers; Sequential circuits; Table lookup;
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-9451-8
DOI :
10.1109/ASPDAC.2006.1594729