Title :
Logic synthesis for automatic layout
Author :
Abouzeid, P. ; Leveugle, R. ; Saucier, G. ; Jamier, R.
Author_Institution :
Inst. Nat. Polytech. de Grenoble, France
Abstract :
The author present an attempt to automate the design of complex modules using a synthesis tool. They aim at generating automatically and directly the layout of a module using complex MOS cells from a behavioural specification. The re-design of the library elements for a new technology would then be replaced by only some changes in the technology files. The two main steps presented in this paper are the decomposition of the initial netlist into complex MOS cells with adequate characteristics and the layout generation for the complex cells
Keywords :
CMOS integrated circuits; MOS integrated circuits; circuit layout CAD; integrated logic circuits; logic CAD; CAD; MOS cells; automatic layout; behavioural specification; complex modules; decomposition; initial netlist; layout generation; technology files; Automatic logic units; Character generation; Electric variables; Equations; Flip-flops; Libraries; MOS devices; MOSFETs; Silicon; Wiring;
Conference_Titel :
Euro ASIC '92, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-2845-6
DOI :
10.1109/EUASIC.1992.228033
