Title :
Toward more advanced usage of instruction level parallelism by a very large data path processor architecture
Author :
Tanaka, Hidehiko
Author_Institution :
Dept. of Electr. Eng., Tokyo Univ., Japan
Abstract :
The architectural performance gain of a microprocessor is going to saturate because of the small gain of instruction level parallelism. In this paper, we discuss the design points and some tentative solutions to overcome this bottleneck and propose a processor architecture called Very Large Data Path. This architecture broadens the window of instruction analysis to extract 10 times of parallel gain compared with the conventional superscaler processors. This paper discusses the system elements and shows some preliminary evaluation results
Keywords :
microprocessor chips; parallel architectures; performance evaluation; instruction analysis; instruction level parallelism; microprocessor; parallel gain; performance gain; processor architecture; very large data path processor; Computer architecture; Data mining; File servers; High performance computing; Home computing; Microcomputers; Parallel processing; Performance gain; Process design; VLIW;
Conference_Titel :
Parallel Architectures, Algorithms, and Networks, 1997. (I-SPAN '97) Proceedings., Third International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-8186-8259-6
DOI :
10.1109/ISPAN.1997.645134
