Title :
A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation
Author :
Onouchi, Masafumi ; Yamada, Tetsuya ; Morikawa, Kimihiro ; Mochizuki, Isamu ; Sekine, Hidetoshi
Author_Institution :
Hitachi Ltd., Tokyo
Abstract :
We have developed a specialized rapid power-estimation methodology for multimedia applications. This methodology has adequate accuracy for the first design of a complicated SoC. For a multimedia application, we developed three methodologies: an IP-level modeling, a power-level adjustment methodology, and a power accumulation methodology. With these methodologies, the system-level power estimation on a SoC executing a practical application becomes so precise and easy that we can revise the SoC design to reduce its power. According to a comparison of the system-level power estimated with these methodologies to board-measured power, the error between the two powers is less than 5.6%
Keywords :
integrated circuit modelling; low-power electronics; system-on-chip; IP-level modeling; SoC design; multimedia applications; power accumulation; power-level adjustment; system-level power estimation; Cellular phones; Digital cameras; Home appliances; Intellectual property; Large scale integration; Multimedia systems; Power dissipation; Power system modeling; System-on-a-chip; TV;
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-9451-8
DOI :
10.1109/ASPDAC.2006.1594742