Title :
Highly manufacturable and high performance SDR/DDR 4 Gb DRAM
Author :
Kim, K.N. ; Jeong, H.S. ; Yang, W.S. ; Hwang, Y.S. ; Cho, C.H. ; Jeong, M.M. ; Park, S. ; Ahn, S.J. ; Chun, Y.S. ; Shin, S.H. ; Park, J.S. ; Song, S.H. ; Lee, J.Y. ; Jang, S.M. ; Lee, C.H. ; Jeong, J.H. ; Cho, K.H. ; Yoon, H.I. ; Jeon, J.S.
Author_Institution :
Samsung Electron. Co., Yongin City, South Korea
Abstract :
A 4 Gb SDR/DDR DRAM is fabricated with 0.11 /spl mu/m CMOS technology. To the best of our knowledge, this is the first working DRAM ever achieved at such a high density. The cell size and chip size of the 4 Gb DRAM are approximately 0.1 /spl mu/m/sup 2/ and 645 mm/sup 2/, respectively. The key technologies developed for this 4 Gb DRAM are KrF lithography with RET, novel ILD gap-filling, full SAC with LSC, novel W-BL, low-temperature Al/sub 2/O/sub 3/ MIS capacitor, and triple level CVD-Al interconnection technology. The key features of these technologies were reported elsewhere (Jeong et al., Tech. Digest of IEDM, pp. 353-6, 2000). The summary of 0.11 /spl mu/m DRAM technology is listed and compared with our previous 0.13 /spl mu/m (Kim et al., 2000) and 0.15 /spl mu/m (Kim et al., 1998) generations. We have found that random single-bit and/or twin-bit failures and block failures are the most critical issues to be solved for achieving good functionality of 4 Gb DRAM. In order to get rid of the single and twin bit failures, 80 nm array transistors, sub-80 nm memory cell contacts and mechanically robust capacitors are developed and triple-level CVD Al technology is optimized to reduce block failure as well as improve chip performance. In this paper, these technologies for achieving good functionality with high performance are highlighted in detail.
Keywords :
CMOS memory circuits; DRAM chips; MIS capacitors; chemical vapour deposition; dielectric thin films; failure analysis; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; integrated circuit reliability; photolithography; 0.11 micron; 0.13 micron; 0.15 micron; 4 Gbit; 80 nm; CMOS technology; DRAM; DRAM density; DRAM technology; ILD gap-filling; KrF lithography; LSC; RET; SAC cell contact; SDR/DDR DRAM; W-BL layer; array transistors; block failure; block failures; cell size; chip performance; chip size; functionality; low-temperature Al/sub 2/O/sub 3/ MIS capacitor; manufacturability; mechanically robust capacitors; memory cell contacts; random single-bit failures; random twin-bit failures; triple level CVD-Al interconnection technology; CMOS technology; Capacitors; Cleaning; Contact resistance; Hydrogen; Lithography; Manufacturing; Plasma temperature; Random access memory; Transistors;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934920
