Impact of scaling on analog/RF CMOS performance

Analog/RF CMOS design in deep-sub micron digital CMOS is particularly challenging due to conflicting device performance requirements. The continuous scaling of digital CMOS has resulted in cut-off frequencies (f_T) above 100Hz. however this improvement comes at a cost of degraded output resistance and reduced intrinsic gain. The difficulty of integrating analog/RF and high-performance digital functions on a single chip are expected to increase with scaling. In particular, it becomes a major issue to maintain analog performance parameters like 1/f noise and matching together with new high-k gate dielectrics. A lower nominal supply voltage is clearly beneficial for designers of digital circuits (lower power consumption, higher speed), but it presents difficult challenges for their analog designer peers. This review article discusses a number of significant items for analog designs in present and future CMOS processes and possible ways to maintain/improve their analog/RF performances. We illustrate the current achievements on a 90 nm CMOS technology and give an overview of the different options opened for future technologies.