Experimental and simulation study on sub-50 nm CMOS design

Author

Pidin, S. ; Shido, H. ; Yamamoto, T. ; Horiguchi, N. ; Kurata, H. ; Sugii, T.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

2001

fDate

12-14 June 2001

Firstpage

35

Lastpage

36

Abstract

CMOS devices with gate lengths down to sub-50 nm were fabricated using poly-Si gates with notches and conventional gate structures. It was shown that an optimal halo, as compared to conventional gates, is achieved when a tilted implant is performed using gates with notches. Due to optimal halo placement, up to 7% improvement in drain current for p-MOS and 15% improvement for n-MOS and simultaneously 20 nm improvement in threshold voltage roll-off were observed for notched gate devices for the same extension implant.

Keywords

CMOS integrated circuits; MOSFET; doping profiles; integrated circuit design; ion implantation; nanotechnology; semiconductor device models; semiconductor device testing; 50 nm; CMOS design; CMOS devices; drain current; extension implant; gate length; gate structures; n-MOSFETs; notched gate devices; notched poly-Si gates; optimal halo implant; optimal halo placement; p-MOSFETs; simulation; threshold voltage roll-off; tilted implant; Analytical models; Boron; Doping; Etching; Fabrication; Implants; Impurities; Laboratories; MOSFET circuits; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934934

Filename

934934