DocumentCode
3261992
Title
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits
Author
Higami, Yoshinobu ; Saluja, Kewal K. ; Takahashi, Hiroshi ; Kobayashi, Shin-ya ; Takamatsu, Yuzo
Author_Institution
Dept. of Comput. Sci., Ehime Univ.
fYear
2006
fDate
24-27 Jan. 2006
Abstract
Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored. The compaction of diagnostic test vectors must take care of all fault pairs that need to be distinguished by a given test vector set. Clearly, the number of fault pairs is much larger than the number of faults thus making this problem very difficult and challenging. The key contributions of this paper are: 1) to use techniques for reducing the size of fault pairs to be considered at a time, 2) to use novel variants of the fault distinguishing table method for combinational circuits and reverse order restoration method for sequential circuits, and 3) to introduce heuristics to manage the space complexity of considering all fault pairs for large circuits. Finally, the experimental results for ISCAS benchmark circuits are presented to demonstrate the effectiveness of the proposed methods
Keywords
combinational circuits; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; ISCAS benchmark circuits; combinational circuits; diagnostic test vectors; fault diagnosis; fault distinguishing table method; fault pairs; reverse order restoration method; sequential circuits; Circuit faults; Circuit testing; Combinational circuits; Compaction; Computer science; Costs; Fault detection; Fault diagnosis; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location
Yokohama
Print_ISBN
0-7803-9451-8
Type
conf
DOI
10.1109/ASPDAC.2006.1594761
Filename
1594761
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