Accurate Formulas for the Capacitance of Tapered-Through Silicon Vias in 3-D ICs

This letter first proposes novel formulas for the calculation of the oxide capacitance and the silicon substrate capacitance in Tapered-Through Silicon vias (T-TSVs). The electric field is non-uniform distribution in T-TSVs due to its non-uniform three-dimensional structure. In order to get accurate formulas for the capacitance of T-TSVs, the conformal mapping method was used properly based on the analytical results of the local electric field structure in T-TSVs. When the slope angle equals to zero, the obtained formulas can be reduced to the formulas of cylindrical TSVs. The comparison between the results of the proposed formulas and the three-dimensional quasi-static field solver shows that the proposed formulas have very high accuracy, with maximum errors of 1% and 3% for the oxide capacitance and the silicon substrate capacitance, respectively.