Active power filters compensator implementation using parallel structures in FPGA devices

This paper presents a parallel implementation approach of selective harmonic compensator for active power filters. This approach uses field programmable gate array (FPGAs) in order to reduce the compensator computational time. To compensate for even a small number of harmonics digital filters require multiple calculation instructions involving multiplications and additions. Thus, to improve the performance of the computer system it is proposed the digital compensator implementation using parallel structures in FPGA devices. Experimental results are presented to compare the speedup of the proposed parallel approach with the DSP sequential execution time conventionally used in active power filters applications.